SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 883

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
When the fault protection is triggered on a channel, the fault protection mechanism forces the
channel outputs to the values defined by the fields FPVHx and FPVLx in the
tion Value Register”
forcing is made asynchronously to the channel counter.
CAUTION:
If a comparison unit is enabled (see
triggered in the channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt
generated at the end of the PWM period) can be generated but only if it is enabled and not
masked. The interrupt is reset by reading the interrupt status register, even if the fault which has
caused the trigger of the fault protection is kept active.
• To prevent an unexpected activation of the status flag FSy in the PWM_FSR register, the
• To prevent an unexpected activation of the Fault Protection on the channel x, the bit FPEx[y]
FMODy bit can be set to “1” only if the FPOLy bit has been previously configured to its final
value.
can be set to “1” only if the FPOLy bit has been previously configured to its final value.
(PWM_FPV) and leads to a reset of the counter of this channel. The output
Section 38.6.3 “PWM Comparison
SAM3U Series
SAM3U Series
Units”) and if a fault is
“PWM Fault Protec-
883
883