SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 168
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.19.3
• CLRENA
Interrupt clear-enable bits.
Write:
0 = no effect
1 = disable interrupt.
Read:
0 = interrupt disabled
1 = interrupt enabled.
168
31
23
15
7
SAM3U Series
Interrupt Clear-enable Registers
30
22
14
6
The ICER0 register disables interrupts, and shows which interrupts are enabled. See:
The bit assignments are:
• the register summary in
•
Table 13-28 on page 166
29
21
13
5
28
20
12
4
Table 13-27 on page 165
for which interrupts are controlled by each register
CLRENA
CLRENA
CLRENA
CLRENA
27
19
11
3
for the register attributes
26
18
10
2
25
17
9
1
6430E–ATARM–29-Aug-11
24
16
8
0
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