SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 445

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.5
Table 26-1.
Note:
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Offset
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
Peripheral DMA Controller (PDC) User Interface
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the desired peripheral.)
Register Mapping
Register
Receive Pointer Register
Receive Counter Register
Transmit Pointer Register
Transmit Counter Register
Receive Next Pointer Register
Receive Next Counter Register
Transmit Next Pointer Register
Transmit Next Counter Register
Transfer Control Register
Transfer Status Register
PERIPH
PERIPH_RNPR
PERIPH_RNCR
PERIPH_TNPR
PERIPH_TNCR
PERIPH_PTCR
PERIPH_PTSR
PERIPH_RCR
PERIPH_TCR
PERIPH_TPR
Name
(1)
_RPR
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Write-only
Read-only
Access
SAM3U Series
SAM3U Series
Reset
0
0
0
0
0
0
0
0
0
0
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