SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 400

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.18 Static Memory Controller (SMC) User Interface
Table 25-11. Register Mapping
400
400
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
0x058
0x05C
0x060
0x064
0x068
0x06C
0x14*CS_number+0x070
0x14*CS_number+0x074
0x14*CS_number+0x078
0x14*CS_number+0x7C
SAM3U Series
SAM3U Series
The SMC is programmed using the fields listed in
registers is used to program the parameters of the external device. In
“CS_number” denotes the chip select number. 16 Bytes per chip select are required.
Register
SMC NFC Configuration Register
SMC NFC Control Register
SMC NFC Status Register
SMC NFC Interrupt Enable Register
SMC NFC Interrupt Disable Register
SMC NFC Interrupt Mask Register
SMC NFC Address Cycle Zero Register
SMC Bank Address Register
SMC ECC Control Register
SMC ECC Mode Register
SMC ECC Status 1 Register
SMC ECC Parity 0 Register
SMC ECC parity 1 Register
SMC ECC status 2 Register
SMC ECC parity 2 Register
SMC ECC parity 3 Register
SMC ECC parity 4 Register
SMC ECC parity 5 Register
SMC ECC parity 6 Register
SMC ECC parity 7 Register
SMC ECC parity 8 Register
SMC ECC parity 9 Register
SMC ECC parity 10 Register
SMC ECC parity 11 Register
SMC ECC parity 12 Register
SMC ECC parity 13 Register
SMC ECC parity 14 Register
SMC ECC parity 15 Register
SMC Setup Register
SMC Pulse Register
SMC Cycle Register
SMC Timings Register
Name
SMC_CFG
SMC_CTRL
SMC_SR
SMC_IER
SMC_ECC_CTRL
SMC_ECC_PR10
SMC_ECC_PR11
SMC_ECC_PR12
SMC_ECC_PR13
SMC_ECC_PR14
SMC_ECC_PR15
SMC_ECC_SR1
SMC_ECC_PR0
SMC_ECC_PR1
SMC_ECC_SR2
SMC_ECC_PR2
SMC_ECC_PR3
SMC_ECC_PR4
SMC_ECC_PR5
SMC_ECC_PR6
SMC_ECC_PR7
SMC_ECC_PR8
SMC_ECC_PR9
SMC_ECC_MD
SMC_TIMINGS
SMC_SETUP
SMC_CYCLE
SMC_PULSE
SMC_ADDR
SMC_BANK
SMC_IMR
SMC_IDR
Table
25-11. For each chip, select a set of 4
Access
Read-write
Write-only
Read-only
Write-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
Reset
0x0
0x0
0x0
0x0
Table
0x01010101
0x01010101
0x00030003
0x00000000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
25-11,