SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 58

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.3.3.1
13.3.3.2
13.3.3.3
13.3.3.4
58
SAM3U Series
General-purpose registers
Stack Pointer
Link Register
Program Counter
Table 13-2.
1.
2.
R0-R12 are 32-bit general-purpose registers for data operations.
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register indi-
cates the stack pointer to use:
On reset, the processor loads the MSP with the value from address 0x00000000.
The Link Register (LR) is register R14. It stores the return information for subroutines, function
calls, and exceptions. On reset, the processor loads the LR value 0xFFFFFFFF
The Program Counter (PC) is register R15. It contains the current program address. Bit[0] is
always 0 because instruction fetches must be halfword aligned. On reset, the processor loads
the PC with the value of the reset vector, which is at address 0x00000004.
Name
FAULTMASK
BASEPRI
CONTROL
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).
Describes access type during program execution in thread mode and Handler mode. Debug
An entry of Either means privileged and unprivileged software can access the register.
access can differ.
Core register set summary (Continued)
Type
RW
RW
RW
(1)
Privileged
Privileged
Privileged
Required
privilege
(2)
Reset
value
0x00000000
0x00000000
0x00000000
Description
“Fault Mask Register” on page 63
“Base Priority Mask Register” on page 64
“CONTROL register” on page 65
6430E–ATARM–29-Aug-11
.