SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1133

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

43.8
Table 43-38. Channel Conversion Time and ADC Clock
Notes:
Table 43-39. External Voltage Reference Input
43.8.1
6430E–ATARM–29-Aug-11
Parameter
ADC Clock Frequency
ADC Clock Frequency
Startup Time
Track and Hold Acquisition Time
Conversion Time
Throughput Rate
Parameter
ADVREF Input Voltage Range
ADVREF Average Current
Current Consumption on VDDCORE
10-bit Successive Approximation Register (SAR) ADC Characteristics
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for
2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for
Sample and Hold Time versus Source Output Impedance
conversion.
conversion
Figure 43-11
Figure 43-11. Simplified Acquisition Path
The user can drive ADC input with impedance up to:
with SHTIM (Sample and Hold Time register) expressed in ns and Z
Note:
• Z
• Z
source
source
Csample and Ron are taken into account in the formulas
≤ (SHTIM -470) x 10 in 8-bit resolution mode
≤ (SHTIM -589) x 7.69 in 10-bit resolution mode
gives a simplified acquisition path.
Conditions
13 samples at ADC Clock = 5MHz
Conditions
10-bit resolution mode
8-bit resolution mode
Return from Idle Mode
ADC Clock = 5MHz
ADC Clock = 8MHz
ADC Clock = 5MHz
ADC Clock = 8MHz
Zsource
Input
ADC
Mux.
Ron
Sample & Hold
Csample
Min
2.4
Min
600
0.55
Typ
200
-
source
Typ
SAM3U Series
ADC
Core
expressed in ohms.
VDDANA+
Max
250
384
533
0.2
Max
1.25
1
20
5
8
2
(1)
(2)
Units
kSPS
Units
MHz
MHz
mA
μs
ns
μs
μA
V
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