SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 291

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.4.6.2
Figure 19-6. NRSTB Reset
Note:
19.4.6.3
19.4.7
19.4.7.1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
32 kHz Low Power Crystal
periph_nreset, ice_reset and proc_nreset are not shown, but are asserted low thanks to the vddcore_nreset signal controlling
the Reset controller.
SHDN / vr_standby
Core Reset
Oscillator output
vddcore_nreset
NRSTB Asynchronous Reset Pin
SHDN output pin
Supply Monitor Reset
bodcore_in
NRSTB
The NRSTB pin is an asynchronous reset input, which acts exactly like the zero-power power-on
reset cell.
As soon as NRSTB is tied to GND, the supply controller is reset generating in turn, a reset of the
whole system.
When NRSTB is released, the system can start as described in
Backup Power
The NRSTB pin does not need to be driven during power-up phase to allow a reset of the sys-
tem, it is done by the zero-power power-on cell.
As shown in
the SHDN pin to control external voltage regulator with shutdown capabilities.
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described
previously in
mally asserted before shutting down the core power supply and released as soon as the core
power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
The supply monitor is capable of generating a reset of the system. This can be enabled by set-
ting the SMRSTEN bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is imme-
diately activated for a minimum of 1 slow clock cycle.
• a supply monitor detection
• a brownout detection
Figure
Section 19.4.6 ”Backup Power Supply
Supply”.
19-6, the SHDN pin acts like the vr_standby signal making it possible to use
30 Slow Clock Cycles = about 1ms
Reset”. The vddcore_nreset signal is nor-
between 2 and 3 Slow Clock Cycles
Section 19.4.6.1 ”Raising the
SAM3U Series
SAM3U Series
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