SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 830

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.8.8.2
830
830
SAM3U Series
SAM3U Series
Block Length is Not Multiple of 4. (ROPT field in HSMCI_DMA register set to 0)
Two DMA Transfer descriptors are used to perform the HSMCI block transfer.
8. Poll CBTC[x] bit in the DMAC_EBCISR Register.
9. If a new list of buffer shall be transferred repeat step 6. Check and handle HSMCI
10. Poll FIFOEMPTY field in the HSMCI_SR.
11. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the
12. Wait for XFRDONE in HSMCI_SR register.
1. Use the previous step to configure the HSMCI to perform a READ_MULTIPLE_BLOCK
2. Issue a READ_MULTIPLE_BLOCK command.
3. Program the DMA Controller to use a list of descriptors.
h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
i.
j.
k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0).
l.
errors.
HSMCI_CMDR.
command.
a. Read the channel register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. For every block of data repeat the following procedure:
d. Program the channel registers in the Memory for the first descriptor. This descriptor
e. The LLI_W(n).DMAC_SADDRx field in memory must be set with the starting
f.
g. Program LLI_W(n).DMAC_CTRLAx with the following field’s values:
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Addresses are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And
set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors
together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to
0.
the LLI Fetch operation.
for request.
reading the DMAC_EBCISR register.
will be word oriented. This descriptor is referred to as LLI_W(n) standing for LLI
word oriented transfer for block n.
address of the HSMCI_FIFO address.
The LLI_W(n).DMAC_DADDRx field in the memory must be word aligned.
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is
Program DMAC_CTRLBx register for channel x with 0. its content is updated with
Enable Channel x writing one to DMAC_CHER[x]. The DMA is ready and waiting
HSMCI Host Controller.
skipped later.
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11