SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 299

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SAM3U2C

Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3U2C

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
19.5.6
Name:
Address:
Access:
• FWUPEN: Force Wake Up Enable
0 (NOT_ENABLE) = the Force Wake Up pin has no wake up effect.
1 (ENABLE) = the Force Wake Up pin low forces the wake up of the core power supply.
• SMEN: Supply Monitor Wake Up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect.
1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect.
1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• FWUPDBC: Force Wake Up Debouncer Period
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
31
23
15
7
Value
0
1
2
3
4
5
6
7
Supply Controller Wake Up Mode Register
SUPC_WUMR
0x400E121C
Read-write
30
22
14
6
32768_SCLK
IMMEDIATE
4096_SCLK
512_SCLK
32_SCLK
Reserved
Reserved
3_SCLK
Name
WKUPDBC
29
21
13
5
Description
Immediate, no debouncing, detected active at least on one Slow Clock edge.
FWUP shall be low for at least 3 SLCK periods
FWUP shall be low for at least 32 SLCK periods
FWUP shall be low for at least 512 SLCK periods
FWUP shall be low for at least 4,096 SLCK periods
FWUP shall be low for at least 32,768 SLCK periods
Reserved
Reserved
28
20
12
4
RTCEN
27
19
11
3
RTTEN
26
18
10
2
FWUPDBC
SAM3U Series
SAM3U Series
SMEN
25
17
9
1
FWUPEN
24
16
8
0
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