SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 76
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SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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13.4.8
76
SAM3U Series
Programming hints for the synchronization primitives
Software can use the synchronization primitives to implement a semaphores as follows:
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has
executed a Load-Exclusive instruction. If the processor is part of a multiprocessor system, the
system also globally tags the memory locations addressed by exclusive accesses by each
processor.
The processor removes its exclusive access tag if:
In a multiprocessor implementation:
For more information about the synchronization primitive instructions, see
on page 114
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide
intrinsic functions for generation of these instructions:
Table 13-8.
The actual exclusive access instruction generated depends on the data type of the pointer
passed to the intrinsic function. For example, the following C code generates the require
LDREXB operation:
Instruction
LDREX, LDREXH, or
LDREXB
STREX, STREXH, or
STREXB
CLREX
• Use a Load-Exclusive instruction to read from the semaphore address to check whether the
• If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
• If the returned status bit from the second step indicates that the Store-Exclusive succeeded
• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means the processor can resolve semaphore conflicts between
• executing a CLREX instruction removes only the local exclusive access tag for the processor
• executing a Store-Exclusive instruction, or an exception. removes the local exclusive access
semaphore is free.
address.
then the software has claimed the semaphore. However, if the Store-Exclusive failed, another
process might have claimed the semaphore after the software performed the first step.
different threads.
tags, and all global exclusive access tags for the processor.
1: No write was performed. This indicates that the value returned the first step might be out
of date. The software must retry the read-modify-write sequence,
__ldrex((volatile char *) 0xFF);
and
C compiler intrinsic functions for exclusive access instructions
“CLREX” on page
Intrinsic function
unsigned int __ldrex(volatile void *ptr)
int __strex(unsigned int val, volatile void *ptr)
void __clrex(void)
116.
“LDREX and STREX”
6430E–ATARM–29-Aug-11
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