SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1022

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

40.2
Figure 40-1. DMA Controller (DMAC) Block Diagram
40.3
40.3.1
1022
Block Diagram
Functional Description
Datapath Bundles
SAM3U Series
DMAC Read
Basic Definitions
DMA FIFO Controller
DMA FIFO
DMA Global Control
DMAC Channel 0
and Data Mux
DMAC Channel 0
Write data path
to destination
DMAC Channel 0
Read data path
from source
Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then
stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form
a channel.
Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previ-
ously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMAC transfer and does not require
a handshaking interface to interact with the DMAC.
Channel: Read/write datapath between a source peripheral on one configured AMBA layer and
a destination peripheral on the same or different AMBA layer that occurs through the channel
Datapath Bundles
DMAC Channel 1
DMAC Write
DMAC Channel 2
DMAC AHB Lite Master Interface
DMAC Channel n
DMAC Destination
Control State Machine
Destination Pointer
Management
DMAC Source
Control State Machine
Source Pointer
Management
AMBA AHB
DMA Destination
Request Arbiter
DMA Global
Requests Pool
DMA Source
Trigger Manager
External
Triggers
Soft
Triggers
APB Interface
Status
Registers
Configuration
Registers
DMAC Interrupt
Controller
DMAC
REQ/ACK
Interface
6430E–ATARM–29-Aug-11
DMAC Interrupt
DMAC
Hardware
Handshaking
Interface
DMAC
APB
Interface