SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 374
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SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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Figure 25-20. TDF Optimization Disabled (TDF Mode = 0). TDF wait states between 2 read accesses on different chip
Figure 25-21. TDF Mode = 0: TDF wait states between a read and a write access on different chip selects
374
374
read1 controlling signal
read2 controlling signal
write2 controlling signal
read1 controlling signal
NBS0, NBS1,
NBS0, NBS1,
SAM3U Series
SAM3U Series
D[15:0]
A[ 23:2]
A0, A1
(NRD)
(NRD)
D[15:0]
A [23:2]
A0, A1
(NWE)
selects
(NRD)
MCK
MCK
TDF_CYCLES = 6
TDF_CYCLES = 4
read1 cycle
read1 cycle
read1 hold = 1
read1 hold = 1
Chip Select Wait State
TDF_CYCLES = 4
Read to Write
Wait State
TDF_CYCLES = 6
Chip Select
Wait State
2 TDF WAIT STATES
5 TDF WAIT STATES
write2 setup = 1
(optimization disabled)
TDF_MODE = 0
write2 cycle
(optimization disabled)
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
TDF_MODE = 0
read2 setup = 1
read 2 cycle
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