SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 55

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SAM3U2C

Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3U2C

Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
13.2.4
13.2.4.1
13.2.4.2
13.2.4.3
13.2.4.4
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
6430E–ATARM–29-Aug-11
Programmers model
Cortex-M3 core peripherals
Processor mode and privilege levels for software execution
Nested Vectored Interrupt Controller
System control block
System timer
Memory protection unit
Thread mode
Handler mode
Unprivileged
These are:
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that sup-
ports low latency interrupt processing.
The System control block (SCB) is the programmers model interface to the processor. It pro-
vides system implementation information and system control, including configuration, control,
and reporting of system exceptions.
The system timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating Sys-
tem (RTOS) tick timer or as a simple counter.
The Memory protection unit (MPU) improves system reliability by defining the memory attributes
for different memory regions. It provides up to eight different regions, and an optional predefined
background region.
This section describes the Cortex-M3 programmers model. In addition to the individual core reg-
ister descriptions, it contains information about the processor modes and privilege levels for
software execution and stacks.
The processor modes are:
Used to execute application software. The processor enters Thread mode when it comes out of
reset.
Used to handle exceptions. The processor returns to Thread mode when it has finished excep-
tion processing.
The privilege levels for software execution are:
The software:
• deterministic, high-performance interrupt handling for time-critical applications
• memory protection unit (MPU) for safety-critical applications
• extensive debug and trace capabilities:
• has limited access to the MSR and MRS instructions, and cannot use the CPS instruction
– Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing.
SAM3U Series
55

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