SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 758

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

35.8.15
Name:
Address:
Access:
This register can only be written if the WPEN bit is cleared in
• TX_PL: Transmitter Preamble Length
0: The Transmitter Preamble pattern generation is disabled
1 - 15: The Preamble Length is TX_PL x Bit Period
• TX_PP: Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
758
758
Value
31
23
15
–
–
–
7
–
00
01
10
11
SAM3U Series
SAM3U Series
USART Manchester Configuration Register
Name
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
DRIFT
30
22
14
US_MAN
0x40090050 (0), 0x40094050 (1), 0x40098050 (2), 0x4009C050 (3)
Read-write
–
–
6
–
Description
The preamble is composed of ‘1’s
The preamble is composed of ‘0’s
The preamble is composed of ‘01’s
The preamble is composed of ‘10’s
29
21
13
1
–
–
5
–
RX_MPOL
TX_MPOL
28
20
12
–
4
–
“USART Write Protect Mode Register” on page
27
19
11
–
–
3
26
18
10
–
–
2
RX_PL
TX_PL
25
17
9
1
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
RX_PP
TX_PP
760.
24
16
8
0