SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1015
SAM3U2C
Manufacturer Part Number
SAM3U2C
Description
Manufacturer
Atmel Corporation
Specifications of SAM3U2C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
96 MHz
Cpu
Cortex-M3
# Of Touch Channels
28
Hardware Qtouch Acquisition
No
Max I/o Pins
57
Ext Interrupts
57
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
4
Twi (i2c)
1
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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39.7.20
Name:
Address:
Access:
Note:
• BUFF_ADD
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access
byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register
END_TR_EN bit is set.
6430E–ATARM–29-Aug-11
6430E–ATARM–29-Aug-11
31
23
15
7
Channel 0 is not used.
UDPHS DMA Channel Address Register
UDPHS_DMAADDRESSx [x = 0..5]
0x400A4304 [0], 0x400A4314 [1], 0x400A4324 [2], 0x400A4334 [3], 0x400A4344 [4], 0x400A4354 [5]
Read-write
30
22
14
6
29
21
13
5
28
20
12
4
BUFF_ADD
BUFF_ADD
BUFF_ADD
BUFF_ADD
27
19
11
3
26
18
10
2
SAM3U Series
SAM3U Series
25
17
9
1
24
16
8
0
1015
1015
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