SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 1163

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

47. Revision History
6430E–ATARM–29-Aug-11
Doc.
Rev.
6430E
Doc.
Rev.
6430D
Comments
Overview:
Comment in front of rows PA24 and PA25 removed, and put as a footnote
Table 11-2, “Multiplexing on PIO Controller A
Figure 5-5 ”Fast Start-Up
blocks.
Wait mode consumption updated in
Clock Generator:
Last sentence removed from
not exist.
Third bullet edited in
Electrical Characteristics:
3 values updated in
Section 43.7.1 ”Gain and Offset Calibration”
SUPC:
Section 19.3.2 ”Slow Clock
to get VDDBU instead of VDDUTMI.
PMC:
Section 28.8 ”Programmable Clock Output
Figure 28-1, “General Clock Block Diagram”
USART:
Section 35. ”Universal Synchronous Asynchronous Receiver Transmitter
instead of DMA.
Errata:
Section 46.2.1.4 ”Flash: Fetching Error after Reading the Unique Identifier”
Comments
Overview:
Section 5.5.2 ”Wait
Section 10.13 ”Chip
TWD1 and TWCK1 removed from
Table 3-1, “Signal Description
A typo fixed in
Section 9.1.1 ”Internal
In the tables that follow, the most recent version of the document appears first.
Note:
Mode”, sentence starting with ‘By configuring...’ --> ‘This is done by configuring...’
Table 43-12, “Typical Current Consumption in Wait
Identification”, (Rev A) was removed from
Section 27.1
Sources”, ‘Falling/Rising Edge Detector’ changed to ‘High/Low Level Detector’ in 3
“rfo” indicates changes requested during document review and approval loop.
Generator”, variable VDD_SUPPLY_MONITOR changed to VDD_Backup, in order
Section 27.5.1 ”Divider and Phase Lock Loop
List”, Note (4) added to TDO Output.
”Description”.
Figure 2-2, “100-pin SAM3U4/2/1C Block
Table 5-1, “Low Power Mode Configuration Summary”
SRAM”: 4224 Kbytes --> 4224 bytes.
Controller”, UPLLCK --> UPLLCK/2.
created.
edited (UPLLCK --> UPLLCK/2, and UPLLDIV /1/2 --> Divider /2)
(PIOA)”, “Peripheral B” column, PA2 and PA17 texts exchanged.
Table
10-1.
Mode”.
(USART)”, PDC condition shown
(3)
Programming”, as PLLADIV2 does
added.
Diagram”.
for TWD1 and TWCK1.
SAM3U Series
Change
Request
Ref.
7724
7954
7922
rfo
7751
7908
rfo
7743
7898
7912
7804
7978
Change
Request
Ref.
7492
7642
7624
7635
7305
1163