SAM3U2C Atmel Corporation, SAM3U2C Datasheet - Page 466

• Manufacturer Part Number: SAM3U2C
• Manufacturer: Atmel Corporation

Specifications of SAM3U2C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 96 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 28
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 57
• Ext Interrupts: 57
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 4
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.2
Figure 28-1. General Clock Block Diagram
28.3
466
XOUT32
(Supply Controller)
Block Diagram
XIN32
XOUT
Master Clock Controller
XIN
SAM3U Series
XTALSEL
Clock Generator
RC Oscillator
12/8/4 MHz
Embedded
Management
Embedded
32 kHz RC
3-20 MHz
Oscillator
32768 Hz
Status
Oscillator
Oscillator
Crystal
Controller
Crystal
Fast
Power
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is
the clock provided to all the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting
the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs.
The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a
Master Clock divider which allows the processor clock to be faster than the Master Clock.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in
PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the
selected clock between 1 and 64, and the division by 3. The PRES field in PMC_MCKR pro-
grams the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in
PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
Control
0
1
0
1
MOSCSEL
USB UTMI
PLLA and
Divider
PLL
UPLL Clock
UPLLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
Slow Clock
SLCK
Divider
UPLLCK/2
/2
MAINCK
PLLACK
SLCK
Master Clock Controller
UPLLCK/2
MAINCK
PLLACK
/1,/2,/3,/4,...,/64
SLCK
MCK
Prescaler
Programmable Clock Controller
/1,/2,/4,...,/64
Prescaler
Sleep Mode
Processor
Clock Controller
Controller
ON/OFF
Divider
Clock
Peripherals
ON/OFF
/8
Free Running Clock
Processor Clock
6430E–ATARM–29-Aug-11
Master Clock
USB Clock
UDPCK
FCLK
HCLK
SysTick
MCK
int
periph_clk[..]
pck[..]