NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 797
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Thermal Sensor Registers (D31:F6)
21.1.24
Intel
®
ICH8 Family Datasheet
PCS—Power Management Control And Status
Address Offset: 54h
Default Value:
31:24
21:16
14:9
7:4
1:0
Bit
23
22
15
8
3
2
Data — RO. Does not apply. Hardwired to 0s.
Bus Power/Clock Control Enable (BPCCE) — RO. Hardwired to 0.
B2/B3 Support (B23) — RO. Does not apply. Hardwired to 0.
Reserved
PME Status (PMES) — RO. This bit is always zero since this PCI Function does not
generate PME#.
Reserved
PME Enable (PMEE) — RO. This bit is always zero since this PCI Function does not
generate PME#.
Reserved
No Soft Reset — RO. When set to 1, this bit indicates that devices transitioning from
D3HOT to D0 because of PowerState commands do not perform an internal reset.
Configuration context is preserved. Upon transition from D3HOT to D0 initialized state,
no additional operating system intervention is required to preserve Configuration
Context beyond writing the PowerState bits.
Reserved
Power State (PS) — R/W. This field is used both to determine the current power
state of the Thermal controller and to set a new power state. The values are:
00 = D0 state
11 = D3
If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
When in the D3
the I/O and memory spaces are not. Additionally, interrupts are blocked.
When software changes this value from the D3 HOT state to the D0 state, no internal
warm (soft) reset is generated.
HOT
0022h
state
–
57h
HOT
states, the Thermal controller’s configuration space is available, but
Description
Attribute:
Size:
R/W, RO
32 bits
797
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