NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 168

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

5.13.5.5
5.13.6
Note:
5.13.6.1
5.13.6.2
5.13.6.3
168
POPDOWN (Auto C2 to C3/C4) (Mobile Only)
After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)
is set, the platform can return to a C3 or C4 state (depending on where it was prior to
going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will
keep the processor in a C2 state until:
Dynamic PCI Clock Control (Mobile Only)
The PCI clock can be dynamically controlled independent of any other low-power state.
This control is accomplished using the CLKRUN# protocol as described in the PCI Mobile
Design Guide, and is transparent to software.
The Dynamic PCI Clock control is handled using the following signals:
The 33 MHz clock to the ICH8 is “free-running” and is not affected by the STP_PCI#
signal.
Conditions for Checking the PCI Clock
When there is a lack of PCI activity, the ICH8 has the capability to stop the PCI clocks
to conserve power. “PCI activity” is defined as any activity that would require the PCI
clock to be running.
Any of the following conditions will indicate that it is not okay to stop the PCI clock:
Behavioral Description
Conditions for Maintaining the PCI Clock
PCI masters or LPC devices that wish to maintain the PCI clock running will observe the
CLKRUN# signal deasserted, and then must re-assert if (drive it low) within 3 clocks.
Conditions for Stopping the PCI Clock
• Bus masters are no longer active.
• A break event occurs. Note that bus master traffic is not a break event in this case.
• CLKRUN#: Used by PCI and LPC peripherals to request the system PCI clock to run
• STP_PCI#: Used to stop the system PCI clock
• Cycles on PCI or LPC
• Cycles of any internal device that would need to go on the PCI bus
• SERIRQ activity
• When there is a lack of activity (as defined above) for 29 PCI clocks, the ICH8
• When the ICH8 has tri-stated the CLKRUN# signal after deasserting it, the ICH8
• After observing the CLKRUN# signal asserted for 1 clock, the ICH8 again starts
• If an internal device needs the PCI bus, the ICH8 asserts the CLKRUN# signal.
• If no device re-asserts CLKRUN# once it has been deasserted for at least 6 clocks,
deasserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
then checks to see if the signal has been re-asserted (externally).
asserting the signal.
the ICH8 stops the PCI clock by asserting the STP_PCI# signal to the clock
synthesizer.
Intel
®
Functional Description
ICH8 Family Datasheet