NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 795
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Thermal Sensor Registers (D31:F6)
21.1.19
21.1.20
21.1.21
Intel
®
ICH8 Family Datasheet
INTPN—Interrupt Pin
Address Offset: 3Dh
Default Value:
TBARB—BIOS Assigned Thermal Base Address
Address Offset: 40h
Default Value:
This BAR creates 4 KB of memory space to signify the base address of Thermal
memory-mapped configuration registers. This memory space is active when
TBARB.SPTYPEN is asserted. This BAR is programmed by BIOS, and allows BIOS to
locate the Thermal registers in system memory space. If both TBAR and TBARB are
programmed, then the OS and BIOS each have their own independent “view” of the
Thermal registers, and must use the TSIU, TCIU, and TBIU registers to denote Thermal
registers ownership/availability.
TBARBH—BIOS Assigned Thermal Base High DWord
Address Offset: 44h
Default Value:
This BAR extension holds the high 32 bits of the 64 bit TBARB.
31:12
11:4
31:0
2:1
7:4
3:0
Bit
Bit
Bit
3
0
Thermal Base Address (TBA) — R/W. This field provides the base address for the
Thermal logic memory-mapped configuration registers; 4 KB are requested by
hardwiring bits 11:4 to 0s.
Reserved
Prefetchable (PREF) — RO. This bit indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG) — RO. This field indicates that this BAR can be located
anywhere in 64 bit address space.
Space Type Enable (SPTYPEN) — R/W. When set to 1b by software, enables the
decode of this memory BAR.
0 = Disable
1 = Enable
Thermal Base Address High (TBAH) — R/W. This field provides TBAR bits 61:32.
Reserved
Interrupt Pin — RO. This field reflects the value of TBD.ZIP in chipset configuration
space.
03h
00000004h
00000000h
–
–
43h
47h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
RO
8 bits
R/W,RO
32 bits
R/W
32 bits
795
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