NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 126

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

5.4.1.3
Table 44.
5.4.1.4
Table 45.
126
Cycle Type / Direction (CYCTYPE + DIR)
The ICH8 always drives bit 0 of this field to 0. Peripherals running bus master cycles
must also drive bit 0 to 0.
Cycle Type Bit Definitions
Size
Bits[3:2] are reserved. The ICH8 always drives them to 00. Peripherals running bus
master cycles are also supposed to drive 00 for bits 3:2; however, the ICH8 ignores
those bits. Bits[1:0] are encoded as listed in
Transfer Size Bit Definition
Bits[3:2]
Bits[1:0]
00
00
10
10
11
00
01
10
11
Bit1
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
a bus master cycle drives this combination, the ICH8 may abort the transfer.
32-bit transfer (4 bytes)
0
1
0
1
x
I/O Read
I/O Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this
value, the Intel
Table 44
®
ICH8 never drives this combination. If a peripheral running
®
shows the valid bit encodings.
ICH8 aborts the cycle.
Table
Size
Definition
45.
Intel
®
Functional Description
ICH8 Family Datasheet