NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 520
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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12.4.1.9
520
EM_CTL—Enclosure Management Control Register (D31:F2)
Address Offset: ABAR + 20h–23h
Default Value:
This register is used to control and obtain status for the enclosure management
interface. This register includes information on the attributes of the implementation,
enclosure management messages supported, the status of the interface, whether any
message are pending, and is used to initiate sending messages. This register is
reserved if enclosure management is not supported (CAP_EMS = ‘0’).
31:27
23:20
15:10
7:1
Bit
26
25
24
19
18
17
16
9
8
0
Reserved
Activity LED Hardware Driven (ATTR.ALHD) — R/WO.
1 = The SATA controller drives the activity LED for the LED message type in hardware
The host controller does not begin transmitting the hardware based activity signal until after
software has written CTL.TM=1 after a reset condition.
Transmit Only (ATTR.XMT) — RO.
0 = The SATA controller supports transmitting and receiving messages.
1 = The SATA controller only supports transmitting messages and does not support
Single Message Buffer (ATTR.SMB) — RO.
0 = There are separate receive and transmit buffers such that unsolicited messages
1 = The SATA controller has one message buffer that is shared for messages to
Reserved
SGPIO Enclosure Management Messages (SUPP.SGPIO): — RO.
1 = The SATA controller supports the SGPIO register interface message type.
SES-2 Enclosure Management Messages (SUPP.SES2): — RO.
1 = The SATA controller supports the SES-2 message type.
SAF-TE Enclosure Management Messages (SUPP.SAFTE): — RO.
1 = The SATA controller supports the SAF-TE message type.
LED Message Types (SUPP.LED): — RO.
1 = The SATA controller supports the LED message type.
Reserved
Reset (RST) — R/WO.
0 = A write of ‘0’ to this bit by software will have no effect.
1 = When set by software, The SATA controller shall reset all enclosure management
Transmit Message (CTL.TM) — R/WO.
0 = A write of ‘0’ to this bit by software will have no effect.
1 = When set by software, The SATA controller shall transmit the message contained
Software shall not change the contents of the message buffer while CTL.TM is set to 1.
Reserved
Message Received (STS.MR) — RO. Message Received is not supported in ICH8.
and does not utilize software for this LED.
receiving messages.
could be supported.
transmit and messages received. Unsolicited receive messages are not supported
and it is software’s responsibility to manage access to this buffer.
message logic and take all appropriate reset actions to ensure messages can be
transmitted / received after the reset. After the SATA controller completes the
reset operation, the SATA controller shall set the value to ‘0’.
in the message buffer. When the message is completely sent, the SATA controller
shall set the value to 0.
07010000h
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W, R/WO, RO
32 bits
Intel
®
ICH8 Family Datasheet
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