NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 714
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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714
19:18
17:15
14:12
11:10
9:4
3:0
Bit
Reserved
L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.
L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon
common-clock configuration.
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6
Active State Link PM Support (APMS) — R/WO. This field indicates what level of
active state link power management is supported on the root port.
Maximum Link Width (MLW) — RO. For the root ports, several values can be taken,
based upon the value of the chipset config register field RPC.PC1 (Chipset Config
Registers:Offset 0224h:bits1:0) for Ports 1-4 and RPC.PC2 (Chipset Config
Registers:Offset 0224h:bits1:0) for Ports 5 and 6
Maximum Link Speed (MLS) — RO. Set to 1h to indicate the link speed is 2.5 Gb/s.
LCLT.CCC
Port #
Port #
Bits
0
1
00b
01b
10b
11b
1
2
3
4
5
6
Neither L0s nor L1 are supported
L0s Entry Supported
L1 Entry Supported
Both L0s and L1 Entry Supported
Value of MLW Field
RPC.PC1=00b
RPC.PC2=00b
Value of EL0 (these bits)
MPC.UCEL (D28:F0/F1/F2/
MPC.CCEL (D28:F0/F1/F2/
01h
01h
01h
01h
01h
01h
F3:D8h:bits20:18)
F3:D8h:bits17:15)
Definition
RPC.PC1=11b
Description
RPC.PC2=11b
04h
01h
01h
01h
N/A
N/A
PCI Express* Configuration Registers
Intel
®
ICH8 Family Datasheet
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