NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 450

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

11.1.4
Note:
450
PCISTS — PCI Status Register (IDE—D31:F1)
Address Offset:
Default Value:
For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
10:9
2:0
Bit
15
14
13
12
11
8
7
6
5
4
3
Detected Parity Error (DPE) — RO. Reserved as 0.
Signaled System Error (SSE) — RO. Reserved as 0.
Received Master Abort (RMA) — R/WC.
0 = Master abort Not generated by Bus Master IDE interface function.
1 = Bus Master IDE interface function, as a master, generated a master abort.
Reserved as 0 — RO.
Reserved as 0 — RO.
DEVSEL# Timing Status (DEV_STS) — RO.
01 = Hardwired; however, the ICH8M does not have a real DEVSEL# signal associated
Data Parity Error Detected (DPED) — RO. Reserved as 0.
Fast Back to Back Capable (FB2BC) — RO. Reserved as 1.
User Definable Features (UDF) — RO. Reserved as 0.
66MHz Capable (66MHZ_CAP) — RO. Reserved as 0.
Reserved
Interrupt Status (INTS) — RO. This bit is independent of the state of the Interrupt
Disable bit in the command register.
0 = Interrupt is cleared.
1 = Interrupt/MSI is asserted.
Reserved
with the IDE unit, so these bits have no effect.
06h
0280h
–
07h
Description
Attribute:
Size:
IDE Controller Registers (D31:F1) (Mobile Only)
16 bits
R/WC, RO
Intel
®
ICH8 Family Datasheet