NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 64

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

Table 10.
64
PCI Interface Signals (Sheet 2 of 3)
REQ1#/ GPIO50
REQ2#/ GPIO52
REQ3#/GPIO54
TRDY#
STOP#
PERR#
IRDY#
REQ0#
Name
PAR
Type
I/O
I/O
I/O
I/O
I/O
I
Initiator Ready: IRDY# indicates the ICH8's ability, as an initiator,
to complete the current data phase of the transaction. It is used in
conjunction with TRDY#. A data phase is completed on any clock
both IRDY# and TRDY# are sampled asserted. During a write,
IRDY# indicates the ICH8 has valid data present on AD[31:0].
During a read, it indicates the ICH8 is prepared to latch data.
IRDY# is an input to the ICH8 when the ICH8 is the target and an
output from the ICH8 when the ICH8 is an initiator. IRDY# remains
tri-stated by the ICH8 until driven by an initiator.
Target Ready: TRDY# indicates the ICH8's ability as a target to
complete the current data phase of the transaction. TRDY# is used
in conjunction with IRDY#. A data phase is completed when both
TRDY# and IRDY# are sampled asserted. During a read, TRDY#
indicates that the ICH8, as a target, has placed valid data on
AD[31:0]. During a write, TRDY# indicates the ICH8, as a target is
prepared to latch data. TRDY# is an input to the ICH8 when the
ICH8 is the initiator and an output from the ICH8 when the ICH8 is
a target. TRDY# is tri-stated from the leading edge of PLTRST#.
TRDY# remains tri-stated by the ICH8 until driven by a target.
Stop: STOP# indicates that the ICH8, as a target, is requesting the
initiator to stop the current transaction. STOP# causes the ICH8, as
an initiator, to stop the current transaction. STOP# is an output
when the ICH8 is a target and an input when the ICH8 is an
initiator.
Calculated/Checked Parity: PAR uses “even” parity calculated on
36 bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the
ICH8 counts the number of one within the 36 bits plus PAR and the
sum is always even. The ICH8 always calculates PAR on 36 bits
regardless of the valid byte enables. The ICH8 generates PAR for
address and data phases and only assures PAR to be valid one PCI
clock after the corresponding address or data phase. The ICH8
drives and tri-states PAR identically to the AD[31:0] lines except
that the ICH8 delays PAR by exactly one PCI clock. PAR is an output
during the address phase (delayed one clock) for all ICH8 initiated
transactions. PAR is an output during the data phase (delayed one
clock) when the ICH8 is the initiator of a PCI write transaction, and
when it is the target of a read transaction. ICH8 checks parity when
it is the target of a PCI write transaction. If a parity error is
detected, the ICH8 will set the appropriate internal status bits, and
has the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives
data that has a parity error. The ICH8 drives PERR# when it detects
a parity error. The ICH8 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via
the PERR# signal).
PCI Requests: The ICH8 supports up to 4 masters on the PCI bus.
REQ[3:1]# pins can instead be used as GPIO.
Description
Intel
®
ICH8 Family Datasheet
Signal Description