NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 384

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

9.8.1.5
384
Cx-STATE_CNF—Cx State Configuration Register
(PM—D31:F0) (Mobile Only)
Offset Address: A9h
Default Value:
Lockable:
Power Well:
This register is used to enable new C-state related modes.
6:5
1:0
Bit
7
4
3
2
SCRATCHPAD (SP) — R/W.
Reserved
Popdown Mode Enable (PDME) — R/W. This bit is used in conjunction with the PUME
bit (D31:F0:A9h, bit 3). If PUME is 0, then this bit must also be 0.
0 = The ICH8 will not attempt to automatically return to a previous C3 or C4 state.
1 = When this bit is a 1 and Intel
NOTE: This bit is separate from the PUME bit to cover cases where latency issues
Popup Mode Enable (PUME) — R/W. When this bit is a 0, the ICH8 behaves like
ICH5, in that bus master traffic is a break event, and it will return from C3/C4 to C0
based on a break event. See
0 = The ICH8 will treat Bus master traffic a break event, and will return from C3/C4 to
1 = When this bit is a 1 and ICH8 observes a bus master request, it will take the
Report Zero for BM_STS (BM_STS_ZERO_EN) — R/W.
0 = The ICH8 sets BM_STS (PMBASE + 00h, bit 4) if there is bus master activity from
1 = When this bit is a 1, ICH8 will not set the BM_STS if there is bus master activity
NOTES:
1.
2.
3.
Reserved
requests, it can return to a previous C3 or C4 state.
C0 based on a break event.
system from a C3 or C4 state to a C2 state and auto enable bus masters. This will
let snoops and memory access occur.
PCI, PCI Express* and internal bus masters.
from PCI, PCI Express and internal bus masters.
permit POPUP but not POPDOWN.
If the BM_STS bit is already set when the BM_STS_ZERO_EN bit is set, the
BM_STS bit will remain set. Software will still need to clear the BM_STS bit.
It is expected that if the PUME bit (this register, bit 3) is set, the
BM_STS_ZERO_EN bit should also be set. Setting one without the other would
mainly be for debug or errata workaround.
BM_STS will be set by LPC DMA or LPC masters, even if BM_STS_ZERO_EN is
set.
00h
No
Core
Chapter 5.13.5
®
ICH8 observes that there are no bus master
Description
Attribute:
Size:
Usage:
for additional details on this mode.
LPC Interface Bridge Registers (D31:F0)
R/W
8-bit
ACPI, Legacy
Intel
®
ICH8 Family Datasheet