NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 792
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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21.1.7
21.1.8
21.1.9
21.1.10
21.1.11
792
SCC—Sub Class Code
Address Offset: 0Ah
Default Value:
BCC—Base Class Code
Address Offset: 0Bh
Default Value:
CLS—Cache Line Size
Address Offset: 0Ch
Default Value:
LT—Latency Timer
Address Offset: 0Dh
Default Value:
HTYPE—Header Type
Address Offset: 0Eh
Default Value:
7:0
7:0
7:0
7:0
6:0
Bit
Bit
Bit
Bit
Bit
7
Sub Class Code (SCC) — RO. Value assigned to ICH8 Thermal logic.
Base Class Code (BCC) — RO. Value assigned to ICH8 Thermal logic.
Cache Line Size (CLS) — RO. Does not apply to PCI Bus Target-only devices.
Latency Timer (LT) — RO. Does not apply to PCI Bus Target-only devices.
Multi-Function Device (MFD) — RO. This bit is 0 because a multi-function device
only needs to be marked as such in Function 0, and the Thermal registers are not in
Function 0.
Header Type (HTYPE) — RO. Implements Type 0 Configuration header.
80h
11h
00h
00h
00h
Description
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Thermal Sensor Registers (D31:F6)
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
RO
8 bits
Intel
®
ICH8 Family Datasheet
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