NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 536
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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536
15:0
Bit
Error (ERR) — R/WC. The ERR field contains error information for use by host
software in determining the appropriate response to the error condition.
If one or more of bits 11:8 of this register are set, the controller will stop the current
transfer.
Bits
15:12
11
10
9
8
7:2
1
0
Description
Reserved
Internal Error (E): The SATA controller failed due to a master or target abort
when attempting to access system memory.
Protocol Error (P): A violation of the Serial ATA protocol was detected.
Note: The ICH8 does not set this bit for all protocol violations that may occur
on the SATA link.
Persistent Communication or Data Integrity Error (C): A communication
error that was not recovered occurred that is expected to be persistent.
Persistent communications errors may arise from faulty interconnect with the
device, from a device that has been removed or has failed, or a number of
other causes.
Transient Data Integrity Error (T): A data integrity error occurred that was
not recovered by the interface.
Reserved
Recovered Communications Error (M): Communications between the
device and host was temporarily lost but was re-established. This can arise
from a device temporarily being removed, from a temporary loss of Phy
synchronization, or from other causes and may be derived from the PhyNRdy
signal between the Phy and Link layers.
Recovered Data Integrity Error (I): A data integrity error occurred that was
recovered by the interface through a retry operation or other recovery action.
Description
SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet
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