NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 303
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Compliant
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Chipset Configuration Registers
7.1.70
7.1.71
Intel
®
ICH8 Family Datasheet
BUC—Backed Up Control Register
Offset Address: 3414–3414h
Default Value:
All bits in this register are in the RTC well and only cleared by RTCRST#.
FD—Function Disable Register
Offset Address: 3418–341Bh
Default Value:
The UHCI functions must be disabled from highest function number to lowest within
each PCI device (Device 29 or Device 26). For example, if only two UHCIs are wanted
on Device 29, software must disable UHCI #3 (UD3 bit set). When disabling UHCIs, the
EHCI Structural Parameters Registers must be updated with coherent information in
“Number of Companion Controllers” and “N_Ports” fields.
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled
function can only be re-enabled by a platform reset.
(Desktop
(Mobile
only)
only)
7:3
Bit
2
1
1
0
Reserved
CPU BIST Enable (CBE) — R/W. This bit is in the resume well and is reset by
RSMRST#, but not PLTRST# nor CF9h writes.
0 = Disabled.
1 = The INIT# signals will be driven active when CPURST# is active. INIT# and
PATA Reset State (PRS) — R/W.
0 = Disabled.
1 = The reset state of the PATA pins will be driven/tri-state.
Reserved
Top Swap (TS) — R/W.
0 = Intel
1 = ICH8 will invert A16 for cycles going to the BIOS space (but not the feature
If ICH8 is strapped for Top-Swap (GNT3# is low at rising edge of PWROK), then this
bit cannot be cleared by software. The strap jumper should be removed and the
system rebooted.
INIT3_3V# will go inactive with the same timings as the other processor
interface signals (hold time after CPURST# inactive).
space) in the FWH.
0000000xb (Desktop)
0000001xb (Mobile)
See bit description
®
ICH8 will not invert A16.
Description
Attribute:
Size:
Attribute:
Size:
R/W
8-bit
R/W, RO
32-bit
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