NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 574
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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14.1.18
14.1.19
574
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset:
Default Value:
CWP—Core Well Policy Register
(USB—D29:F0/F1/F2, D26:F0/F1)
Address Offset: C8h
Default Value:
7:2
7:1
Bit
Bit
1
0
0
Reserved
PORT1EN — R/W. Enable port 1 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
PORT0EN — R/W. Enable port 0 of the USB controller to respond to wakeup events.
0 = The USB controller will not look at this port for a wakeup event.
1 = The USB controller will monitor this port for remote wakeup and connect/
Reserved
Static Bus Master Status Policy Enable (SBMSPE) — R/W.
0 = The UHCI host controller dynamically sets the Bus Master status bit (Power
1 = The UHCI host controller statically forces the Bus Master Status bit in power
NOTE: The PCI Power Management registers are enabled in the PCI Device 31:
disconnect events.
disconnect events.
Management 1 Status Register,[PMBASE+00h], bit 4) based on the memory
accesses that are scheduled. For mobile components, the default setting provides a
more accurate indication of snoopable memory accesses in order to help with
software-invoked entry to C3 and C4 power states.
management space to 1 whenever the HCHalted bit (USB Status Register,
Base+02h, bit 5) is cleared.
Function 0 space (PM_IO_EN), and can be moved to any I/O location (128-byte
aligned).
00h
C4h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W
8 bits
UHCI Controllers Registers
Intel
®
ICH8 Family Datasheet
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