NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 725
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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PCI Express* Configuration Registers
18.1.45
Intel
®
ICH8 Family Datasheet
MPC—Miscellaneous Port Configuration Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: D8h
Default Value:
23:21
20:18
Bit
31
30
29
28
27
26
25
24
Power Management SCI Enable (PMCE) — R/W.
0 = Disable. SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is
Hot Plug SCI Enable (HPCE) — R/W.
0 = Disable. SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Link Hold Off (LHO): When set, the port will not take any TLP. This is used during
loopback mode to fill up the downstream queue.
Address Translator Enable (ATE): Used to enable address translation via the AT bits
in this register during loopback mode.
Lane Reversal (LR) — RO. This register reads the setting of the SATALED# strap.
0 = PCI Express Lanes 0–3 are reversed.
1 = No Lane reversal (default).
NOTES:
1.
2.
Invalid Receive Bus Number Check Enable (IRBNCE): When set, the receive
transaction layer will signal an error if the bus number of a Memory request does not
fall within the range between SCBN and SBBN. If this check is enabled and the request
is a memory write, it is treated as an Unsupported Request. If this check is enabled and
the request is a non-posted memory read request, the request is considered a
Malformed TLP and a fatal error.
Messages, IO, Configuration, and Completions are never checked for valid bus number.
Invalid Receive Range Check Enable (IRRCE): When set, the receive transaction
layer will treat the TLP as an Unsupported Request error if the address range of a
Memory request does not outside the range between prefetchable and non-prefetchable
base and limit.
Messages, I/O, Configuration, and Completions are never checked for valid address
ranges.
BME Receive Check Enable (BMERCE): When set, the receive transaction layer will
treat the TLP as an Unsupported Request error if a memory read or write request is
received and the Bus Master Enable bit is not set.
Messages, I/O, Configuration, and Completions are never checked for BME.
Reserved
Unique Clock Exit Latency (UCEL) — R/W. This value represents the L0s Exit
Latency for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/
F5:Offset 50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by
BIOS.
detected.
The port configuration straps must be set such that Port 1 is configured as a x4
port using lanes 0–3 when Lane Reversal is enabled. x2 lane reversal is not
supported.
This register is only valid on port 1.
08110000h
–
DBh
Description
Attribute:
Size:
R/W, RO
32 bits
725
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