NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 531

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet
12:8
7:5
Bit
13
4
3
2
1
0
Interlock Switch State (ISS) — RO. For systems that support interlock switches
(via CAP.SIS [ABAR+00h:bit 28]), if an interlock switch exists on this port (via ISP
in this register), this bit indicates the current state of the interlock switch. A 0
indicates the switch is closed, and a 1 indicates the switch is opened.
For systems that do not support interlock switches, or if an interlock switch is not
attached to this port, this bit reports 0.
Current Command Slot (CCS) — RO. Indicates the current command slot the
ICH8 is processing. This field is valid when the ST bit is set in this register, and is
constantly updated by the ICH8. This field can be updated as soon as the ICH8
recognizes an active command slot, or at some point soon after when it begins
processing the command.
This field is used by software to determine the current command issue location of
the ICH8. In queued mode, software shall not use this field, as its value does not
represent the current command being executed. Software shall only use PxCI and
PxSACT when running queued commands.
Reserved
FIS Receive Enable (FRE) — R/W. When set, the ICH8 may post received FISes
into the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and
PxFBU (ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not
accepted by the ICH8, except for the first D2H (device-to-host) register FIS after
the initialization sequence.
System software must not set this bit until PxFB (PxFBU) have been programmed
with a valid pointer to the FIS receive area, and if software wishes to move the
base, this bit must first be cleared, and software must wait for the FR bit (bit 14)
in this register to be cleared.
Command List Override (CLO) — R/W. Setting this bit to '1' causes PxTFD.STS.BSY
and PxTFD.STS.DRQ to be cleared to '0'. This allows a software reset to be
transmitted to the device regardless of whether the BSY and DRQ bits are still set
in the PxTFD.STS register. The HBA sets this bit to '0' when PxTFD.STS.BSY and
PxTFD.STS.DRQ have been cleared to '0'. A write to this register with a value of '0'
shall have no effect.
This bit shall only be set to '1' immediately prior to setting the PxCMD.ST bit to 1
from a previous value of 0. Setting this bit to 1 at any other time is not supported
and will result in indeterminate behavior. Software must wait for CLO to be cleared
to 0 before setting PxCMD.ST to 1.
Power On Device (POD) — RO. Cold presence detect not supported. Defaults to 1.
Spin-Up Device (SUD) — R/W / RO
This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W
when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not
support staggered spin-up (when CAP.SSS is 0).
0 = No action.
1 = On an edge detect from 0 to 1, the ICH8 starts a COMRESET initialization
Clearing this bit to 0 does not cause any OOB signal to be sent on the interface. When this bit
is cleared to 0 and PxSCTL.DET=0h, the HBA will enter listen mode.
Start (ST) — R/W. When set, the ICH8 may process the command list. When
cleared, the ICH8 may not process the command list. Whenever this bit is changed
from a 0 to a 1, the ICH8 starts processing the command list at entry 0. Whenever
this bit is changed from a 1 to a 0, the PxCI register is cleared by the ICH8 upon
the ICH8 putting the controller into an idle state.
Refer to Section 12.2.1 of the Serial ATA AHCI Specification for important
restrictions on when ST can be set to 1.
sequence to the device.
Description
531