NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 366

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

9.5.5
9.5.6
366
ID—Identification Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
VER—Version Register (LPC I/F—D31:F0)
Index Offset:
Default Value:
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
31:28
27:24
23:16
31:24
23:16
14:0
14:8
7:0
Bit
Bit
15
15
Reserved
APIC ID — R/W. Software must program this value before using the APIC.
Reserved
Scratchpad Bit.
Reserved
Reserved
Maximum Redirection Entries — RO. This is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the ICH8 this field
is hardwired to 17h to indicate 24 interrupts.
PRQ — RO. Indicate that the IOxAPIC does not implement the Pin Assertion Register.
Reserved
Version — RO. This is a version number that identifies the implementation version.
00h
00000000h
01h
00170020h
Description
Description
Attribute:
Size:
Attribute:
Size:
LPC Interface Bridge Registers (D31:F0)
R/W
32 bits
RO
32 bits
Intel
®
ICH8 Family Datasheet