NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 180
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Table 74.
5.13.10.3
Table 75.
5.13.11
5.13.11.1
180
PIC Reserved Bits Return Values
Read Only Registers with Write Paths in ALT Access Mode
The registers described in
Software restores these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Register Write Accesses in ALT Access Mode
System Power Supplies, Planes, and Signals
Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5# and SLP_M#
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the STR state (typically mapped to ACPI S3). Power must be
maintained to the ICH8 resume well, and to any other circuits that need to generate
Wake signals from the STR state.
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard.
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done via the power supply, or
by external FETs to the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to
the motherboard.
SLP_M# output signal can be used to cut power to the Link Controller, Clock chip or SPI
flash on a platform that supports Intel AMT.
I/O Address
PIC Reserved Bits
D0h
08h
OCW2(4:3)
OCW3(4:3)
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
OCW3(7)
OCW3(5)
ICW4(0)
DMA Status Register for channels 0–3.
DMA Status Register for channels 4–7.
Register Write Value
Table 75
Value Returned
Reflects bit 6
000
000
00
00
01
0
0
have write paths to them in ALT access mode.
Intel
®
Functional Description
ICH8 Family Datasheet
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