NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 659
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Intel
17.1.35
17.1.36
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
DEVS—Device Status Register
(Intel
Address Offset: 7Ah-7Bh
Default Value:
VCCAP—Virtual Channel Enhanced Capability Header
(Intel
Address Offset: 100h-103h
Default Value:
31:20
19:16
15:6
15:0
Bit
Bit
5
4
3
2
1
0
Reserved
Transactions Pending — RO.
0 = Completions for all non-posted requests have been received
1 = Intel
AUX Power Detected — RO. Hardwired to 1 indicating the device is connected to resume
power
Unsupported Request Detected — RO. Not implemented. Hardwired to 0.
Fatal Error Detected — RO. Not implemented. Hardwired to 0.
Non-Fatal Error Detected — RO. Not implemented. Hardwired to 0.
Correctable Error Detected — RO. Not implemented. Hardwired to 0.
Next Capability Offset — RO. Hardwired to 130h. Points to the next capability header,
which is the Root Complex Link Declaration Enhanced Capability Header.
Capability Version — RO. Hardwired to 1h.
PCI Express* Extended Capability — RO. Hardwired to 0002h.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
not been completed.
®
0010h
13010002h
High Definition Audio controller has issued non-posted requests that have
Description
Description
Attribute:
Size:
Attribute:
Size:
RO
16 bits
RO
32 bits
659
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