NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 315
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Gigabit LAN Configuration Registers
8.1.12
8.1.13
8.1.14
Intel
®
ICH8 Family Datasheet
MBARC—Memory Base Address Register C
(Gigabit LAN—D25:F0)
Address Offset: 18h
Default Value:
Internal registers, and memories, can be accessed using I/O operations. There are two
4B registers in the IO mapping window: Addr Reg and Data Reg. SW may only access a
Dword at a time.
SID—Subsystem ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Ch
Default Value:
SVID—Subsystem Vendor ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Eh
Default Value:
31:5
15:0
15:0
4:1
Bit
Bit
Bit
0
Base Address (BA) — R/W. Software programs this field with the base address of
this region.
I/O Size (IOSIZE) — RO. I/O space size is 32 Bytes.
Memory / IO Space (MIOS) — RO. Set to ‘1’ indicating an IO Space BAR.
Subsystem ID (SID) — RO. This value may be loaded automatically from the NVM
Word 0Ch upon power up depending on the "Load Subsystem ID" bit field in NVM word
0Ah. A value of 8086h is default for this field upon power up if the NVM does not
respond or is not programmed. All functions are initialized to the same value.
Subsystem Vendor ID (SVID) — RO. This value may be loaded automatically from the
NVM Word 0Bh upon power up or reset depending on the "Load Subsystem ID" bit field
in NVM word 0Ah with a default value of 0000h. This value is loadable from NVM word
location 0Bh.
00000000h
See bit description
See bit description
–
–
–
1Bh
2Fh
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W, RO
32 bits
RO
16 bits
RO
16 bits
315
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