NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 417
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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LPC Interface Bridge Registers (D31:F0)
9.9.2
9.9.3
9.9.4
Intel
®
ICH8 Family Datasheet
TCO_DAT_IN—TCO Data In Register
I/O Address:
Default Value:
Lockable:
TCO_DAT_OUT—TCO Data Out Register
I/O Address:
Default Value:
Lockable:
TCO1_STS—TCO1 Status Register
I/O Address:
Default Value:
Lockable:
15:13
7:0
7:0
Bit
Bit
Bit
12
11
10
9
TCO Data In Value — R/W. This data register field is used for passing commands from
the OS to the SMI handler. Writes to this register will cause an SMI and set the
SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).
TCO Data Out Value — R/W. This data register field is used for passing commands
from the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in
the TCO_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL
bits.
Reserved
DMISERR_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to
Reserved
DMISMI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to
DMISCI_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = ICH8 received a DMI special cycle message via DMI indicating that it wants to
cause an SERR#. The software must read the (G)MCH to determine the reason for
the SERR#.
cause an SMI. The software must read the (G)MCH to determine the reason for the
SMI.
cause an SCI. The software must read the (G)MCH to determine the reason for the
SCI.
TCOBASE +02h
00h
No
TCOBASE +03h
00h
No
TCOBASE +04h
0000h
No
Description
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
R/W
R/WC, RO
8-bit
Core
8-bit
Core
16-bit
Core
(Except bit 7, in RTC)
417
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