NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 655
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Intel
17.1.26
17.1.27
Intel
®
®
ICH8 Family Datasheet
High Definition Audio Controller Registers (D27:F0)
MID—MSI Capability ID Register
(Intel
Address Offset: 60h-61h
Default Value:
MMC—MSI Message Control Register
(Intel
Address Offset: 62h-63h
Default Value:
15:8
15:8
1:0
7:0
6:4
3:1
Bit
Bit
Bit
7
0
Power State (PS) — R/W. This field is used both to determine the current power state
of the Intel High Definition Audio controller and to set a new power state.
00 = D0 state
11 = D3
Others = reserved
NOTES:
1.
2.
3.
Next Capability (Next) — RO. Hardwired to 70h. Points to the PCI Express* capability
structure.
Cap ID (CAP) — RO. Hardwired to 05h. Indicates that this pointer is a MSI capability
Reserved
64b Address Capability (64ADD) — RO. Hardwired to 1. Indicates the ability to generate
a 64-bit message address
Multiple Message Enable (MME) — RO. Normally this is a R/W register. However, since
only 1 message is supported, these bits are hardwired to 000 = 1 message.
Multiple Message Capable (MMC) — RO. Hardwired to 0 indicating request for 1
message.
MSI Enable (ME) — R/W.
0 = MSI may not be generated
1 = MSI will be generated instead of an INTx signal.
®
®
High Definition Audio Controller—D27:F0)
High Definition Audio Controller—D27:F0)
If software attempts to write a value of 01b or 10b in to this field, the write
operation must complete normally; however, the data is discarded and no state
change occurs.
When in the D3
configuration space is available, but the I/O and memory space are not.
Additionally, interrupts are blocked.
When software changes this value from D3
warm (soft) reset is generated, and software must re-initialize the function.
HOT
7005h
0080h
state
HOT
states, the Intel High Definition Audio controller’s
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
HOT
state to the D0 state, an internal
RO
16 bits
RO, R/W
16 bits
655
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