NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 532
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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12.4.2.8
12.4.2.9
532
PxTFD—Port [5:0] Task File Data Register (D31:F2)
Address Offset: Port 0: ABAR + 120h
Default Value:
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are:
D2H Register FIS
PIO Setup FIS
Set Device Bits FIS
PxSIG—Port [5:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h
Default Value:
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
31:16
15:8
31:0
7:0
Bit
Bit
Reserved
Error (ERR) — RO. Contains the latest copy of the task file error register.
Status (STS) — RO. Contains the latest copy of the task file status register. Fields of
note in this register that affect AHCI.
Signature (SIG) — RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
31:24
23:16
15:8
6:4
2:1
7:0
Bit
Bit
7
3
0
Port 1: ABAR + 1A0h
Port 2: ABAR + 220h
Port 3: ABAR + 2A0h (Desktop Only)
Port 4: ABAR + 320h (Desktop Only)
Port 5: ABAR + 3A0h (Desktop Only)
0000007Fh
Port 1: ABAR + 1A4h
Port 2: ABAR + 224h
Port 3: ABAR + 2A4h (Desktop Only)
Port 4: ABAR + 324h (Desktop Only)
Port 5: ABAR + 3A4h (Desktop Only)
FFFFFFFFh
Field
LBA High Register
LBA Mid Register
LBA Low Register
Sector Count Register
Field
DRQ
BSY
ERR
N/A
N/A
Definition
Indicates the interface is busy
Not applicable
Indicates a data transfer is requested
Not applicable
Indicates an error during the transfer
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
RO
32 bits
RO
32 bits
Intel
®
ICH8 Family Datasheet
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