NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 488

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

488
Bits
7:6
8
5
4
3
2
1
0
Port 0 Present (P0P) — RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled via P0E. This bit is not cleared upon surprise removal
of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
Reserved
Port 5 Enabled (P5E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P5CMD.SUD (offset ABAR+298h:bit 1)
Port 4 Enabled (P4E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P4CMD.SUD (offset ABAR+298h:bit 1)
Port 3 Enabled (P3E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1)
Port 2 Enabled (P2E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1)
Port 1 Enabled (P1E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1)
Port 0 Enabled (P0E) — R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1)
can detect devices.
can detect devices.
can detect devices.
can detect devices.
can detect devices.
can detect devices.
Description
SATA Controller Registers (D31:F2)
Intel
®
ICH8 Family Datasheet