NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 742
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
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Table 142.
19.1.1
742
Memory-Mapped Registers (Sheet 2 of 2)
NOTES:
1.
2.
GCAP_ID—General Capabilities and Identification Register
Address Offset: 00h
Default Value:
140–147h
148–14Fh
150–15Fh
160–3FFh
63:32
31:16
12:8
Offset
7:0
Bit
15
14
13
Reads to reserved registers or bits will return a value of 0.
Software must not attempt locks to the memory-mapped I/O ranges for High Precision
conditions may occur.
Event Timers. If attempted, the lock is not honored, which means potential deadlock
Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the
period at which the counter increments in femptoseconds (10^-15 seconds). This will
return 0429B17F when read. This indicates a period of 69841279 fs (69.841279 ns).
Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to
Intel.
Replacement Interrupt Rout option is supported.
Reserved. This bit returns 0 when read.
Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit
wide.
Number of Timer Capability (NUM_TIM_CAP) — RO. This field indicates the number of
timers in this block.
02h = Three timers.
Revision Identification (REV_ID) — RO. This indicates which revision of the function is
implemented. Default value will be 01h.
Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy
TIM2_COMP
TIM2_CONF
Mnemonic
0429B17F8086A201h
—
—
Timer 2 Configuration and Capabilities
Timer 2 Comparator Value
Reserved
Reserved
Register
Description
Attribute:
Size:
High Precision Event Timer Registers
RO
64 bits
Intel
N/A
N/A
—
—
Default
®
ICH8 Family Datasheet
R/W, RO
R/W
—
—
Type
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