NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 289
NH82801HEM S LB9B
Manufacturer Part Number
NH82801HEM S LB9B
Description
Manufacturer
Intel
Datasheet
1.NH82801HEM_S_LB9B.pdf
(890 pages)
Specifications of NH82801HEM S LB9B
Lead Free Status / RoHS Status
Compliant
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Chipset Configuration Registers
7.1.53
7.1.54
Intel
®
ICH8 Family Datasheet
D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h
Default Value:
D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh
Default Value:
31:28
27:12
31:4
11:8
3:0
7:4
3:0
Bit
Bit
Reserved
PCI Bridge Pin (LIP) — RO. Currently, the PCI bridge does not generate an interrupt,
so this field is read-only and 0.
EHCI Pin (EIP) — R/W. This field indicates which pin the EHCI controller drives as
its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
Reserved
UHCI #2 Pin (U2P) — R/W. This field indicates which pin the UHCI controller #2
(ports 4 and 5) drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–7h = Reserved
UHCI #1 Pin (U1P) — R/W. This field indicates which pin the UHCI controller #1
(ports 2 and 3) drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
UHCI #0 Pin (U0P) — R/W. This field indicates which pin the UHCI controller #0
(ports 0 and 1) drives as its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
00000000h
10004321h
Description
Description
Attribute:
Size:
Attribute:
Size:
R/W, RO
32-bit
R/W
32-bit
289
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