NH82801HEM S LB9B Intel, NH82801HEM S LB9B Datasheet - Page 104

• Manufacturer Part Number: NH82801HEM S LB9B
• Manufacturer: Intel

Specifications of NH82801HEM S LB9B

• Lead Free Status / RoHS Status: Compliant

Table 35.
Table 36.
104
PERp[6:1], PERn[6:1]
LDRQ1# / GPIO23
REQ1/GPIO50
REQ2/GPIO52
REQ3/GPIO53
GPIO[7,6,1,17]
Signal Name
DMI[3:0]RXP,
DMI[3:0]RXN
Signal Name
DMI_CLKN
GLAN_CLK
DMI_CLKP
TACH[3:0]/
LDRQ0#
SPI_MISO
REQ0#,
PCICLK
SERR#
Power Plane for Input Signals for Desktop Configurations (Sheet 3 of 3)
NOTES:
1.
2.
3.
Power Plane for Input Signals for Mobile Configurations (Sheet 1 of 3)
PME#
CLK14
CLK48
The state of the DPRSLPVR and DPRSTP# signals in C4 are high if Deeper Sleep is enabled
glitch free immediately after Reset until the time they are initialized as GPIO.
These signals can be configured as outputs in GPIO mode.
or low if it is disabled.
GPIO50, GPIO52, GPIO54 need to be glitch free immediately after Reset to when they are
being initialized to GPIO. Multiplexed GPIO signals defaulting to a native function must be
1, 3
1, 3
1, 3
1
1
Suspend
Suspend
Power Well
Power
Well
Core
Core
Core
Core
Core
Core
Core
Core
Suspend
Core
Core
Core
Platform LAN Connect Interface
Driver During Reset
PCI Express* Device
PCI Bus Peripherals
Fan Speed Control
Clock Generator
Clock Generator
External Pull up
Internal Pull-up
LAN Connect
SPI Interface
LPC Interface
LPC Devices
LPC Devices
Driver During Reset
Component
PCI Express
(G)MCH
PCI Bus
External Pull-up
Clock Generator
Clock Generator
Internal Pull-up
Clocks
DMI
Running
Running
C3/C4
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Driven
Running
Running
Driven
Driven
S1
Running
Running
Driven
Driven
Driven
Driven
Driven
High
High
High
S1
Intel
®
Intel
Driven
ICH8 Family Datasheet
S3
Off
Off
Off
Driven
Driven
®
S3
Off
Off
Off
Off
Off
Off
Off
Off
ICH8 Pin States
S4/S5
Driven
S4/S5
Driven
Driven
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off