UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 76

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
3.4 Operand Address Addressing
during instruction execution.
3.4.1 Implied addressing
74
[Function]
The following methods are available to specify the register and memory (addressing) to undergo manipulation
[Operand format]
[Description example]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/KE1+ instruction words, the following instructions employ implied addressing.
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
In the case of MULU X
With an 8-bit
the A and AX registers are specified by implied addressing.
MULU
DIVUW
ADJBA/ADJBS
ROR4/ROL4
Instruction
8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
A register for storage of numeric values that become decimal correction targets
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
A register for storage of digit data that undergoes digit rotation
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16899EJ3V0UD
Register to Be Specified by Implied Addressing

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