UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 404

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
operation. Even if CLME is set to 1 by software during the oscillation stabilization time (reset value of OSTS register
is 05H (2
the high-speed system clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.
402
High-speed system clock
Internal oscillation clock
Internal oscillation clock
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
(CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time)
Internal reset signal
Clock monitor status
16
CPU operation
/f
system clock
XP
High-speed
)) of the high-speed system clock, monitoring is not performed until the oscillation stabilization time of
(1) When internal reset is executed by oscillation stop of high-speed system clock
CLMRF
CLME
RESET
CLME
Monitoring
operation
Normal
(2) Clock monitor status after RESET input
Figure 21-3. Timing of Clock Monitor (1/4)
Oscillation
Oscillation
stopped
stopped
Reset
CHAPTER 21 CLOCK MONITOR
User’s Manual U16899EJ3V0UD
4 clocks of internal oscillation clock
Clock supply
17 clocks
Monitoring stopped
stopped
Oscillation stabilization time
Set to 1 by software
Normal operation (internal oscillation clock)
stabilization time
Waiting for end
of oscillation
Monitoring

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