UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 303
UPD78F0138HGK-9ET-A
Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet
1.UPD78F0138HGK-9ET-A.pdf
(568 pages)
Specifications of UPD78F0138HGK-9ET-A
Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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<R>
(4) Clock selection register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Notes 1.
Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the
Symbol
CKSR6
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
2.
2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Be sure to set the base clock so that the following condition is satisfied.
Note the following points when selecting the TM50 output as the base clock.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
TPS63
V
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty
= 50%.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
V
V
V
clock of the internal oscillator is divided and supplied as the count clock. If the base clock is
the internal oscillation clock, the operation of serial interface UART6 is not guaranteed.
DD
7
0
0
0
0
0
0
0
0
0
1
1
1
1
DD
DD
DD
= 2.5 to 2.7 V: Base clock
= 4.0 to 5.5 V: Base clock
= 3.3 to 4.0 V: Base clock
= 2.7 to 3.3 V: Base clock
Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
TPS62
Other than above
6
0
0
0
0
0
1
1
1
1
0
0
0
0
CHAPTER 14 SERIAL INTERFACE UART6
TPS61
5
0
0
0
1
1
0
0
1
1
0
0
1
1
User’s Manual U16899EJ3V0UD
2.5 MHz (standard products, (A) grade products only)
10 MHz
8.38 MHz
5 MHz
TPS60
4
0
0
1
0
1
0
1
0
1
0
1
0
1
f
f
f
f
f
f
f
f
f
f
f
TM50 output
Setting prohibited
X
X
X
X
X
X
X
X
X
X
X
/2 (5 MHz)
/2
/2
/2
/2
/2
/2
/2
/2
/2
(10 MHz)
TPS63
2
3
4
5
6
7
8
9
10
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(312.5 kHz)
(156.25 kHz)
(78.13 kHz)
(39.06 kHz)
(19.53 kHz)
3
(9.77 kHz)
Base clock (f
Note 2
TPS62
2
XCLK6
) selection
TPS61
1
Note 1
TPS60
0
301
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