UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 423

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

24.2 Format of Option Byte
Address: 0080H/1080H
Address: 0081H/1081H, 0082H/1082H, 0083H/1083H
Address: 0084H/1084H
The format of the option byte is shown below.
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
Cautions 1. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
Note Be sure to set 00H to 0081H, 0082H, and 0083H, as these addresses are reserved areas. Also set 00H to
Notes 1.
Remark For the on-chip debug security ID, see CHAPTER 27 ON-CHIP DEBUG FUNCTION ( PD78F0138HD
boot swap operation.
1081H, 1082H, and 1083H because 0081H, 0082H, and 0083H are switched with 1081H, 1082H, and
1083H when the boot swap operation is used.
2.
ONLY).
2. Be sure to clear bit 1 to 7 to 0.
Be sure to set 00H (on-chip debug operation disabled) to 0084H for products not equipped with the on-
chip debug function ( PD78F0132H, 78F0133H, 78F0134H, 78F0136H, and 78F0138H). Also set
00H to 1084H because 0084H and 1084H are switched at boot swapping.
To use the on-chip debug function with a product equipped with the on-chip debug function
( PD78F0138HD), set 02H or 03H to 0084H. Set a value that is the same as that of 0084H to 1084H
because 0084H and 1084H are switched at boot swapping.
LSROSC
OCDEN1
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (RSTOP) of
the internal oscillation mode register (RCM).
When 8-bit timer H1 operates with the internal oscillation clock, the count clock is supplied to
8-bit timer H1 even in the HALT/STOP mode.
7
0
0
1
7
0
7
0
0
0
1
1
Note
Notes1, 2
Can be stopped by software (stopped when 1 is written to bit 0 (RSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to RSTOP bit)
OCDEN0
6
0
6
0
6
0
0
1
0
1
Operation disabled
Setting prohibited
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
Figure 24-1. Format of Option Byte
CHAPTER 24 OPTION BYTE
5
0
5
0
5
0
User’s Manual U16899EJ3V0UD
Note
4
0
4
0
4
0
Internal oscillator operation
On-chip debug operation control
3
0
3
0
3
0
2
0
2
0
2
0
OCDEN1
1
0
1
0
1
LSROSC
OCDEN0
0
0
0
0
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