UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 286

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

284
R
X
D0/SI10/P11
(e) Reception error
(f) Noise filter of receive data
Parity error
Framing error
Overrun error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt request (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt servicing (INTSR0) (see Figure 13-3).
The contents of ASIS0 are reset to 0 when ASIS0 is read.
The R
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 13-10, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
Reception Error
X
D0 signal is sampled using the base clock output by the prescaler block.
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
In
CHAPTER 13 SERIAL INTERFACE UART0
Table 13-3. Cause of Reception Error
Figure 13-10. Noise Filter Circuit
Q
User’s Manual U16899EJ3V0UD
Internal signal A
Match detector
Cause
In
LD_EN
Q
Internal signal B