UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 353

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Address: FF66H, FF67H
Symbol
MDB0
(3) Multiplication/division data register B0 (MDB0)
Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
The functions of MDA0 when an operation is executed are shown in the table below.
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider
control register 0 (DMUC0) is set to 1.
MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the
division mode.
This register can be set by an 8-bit or 16-bit memory manipulation instruction.
RESET input clears this register to 0000H.
Register configuration during multiplication
MDA0 (bits 15 to 0)
Register configuration during division
MDA0 (bits 31 to 0)
MDB
015
DMUSEL0
<Multiplier A>
<Dividend>
2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are
0
1
multiplier/divider control register 0 (DMUC0) is 1).
executed, but the result is undefined.
stored in MDA0 and SDR0.
MDB
014
Figure 16-4. Format of Multiplication/Division Data Register B0 (MDB0)
MDB
013
Table 16-2. Functions of MDA0 During Operation Execution
After reset: 0000H
FF67H (MDB0H)
Division mode
Multiplication mode
MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0)
MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) … SDR0 (bits 15 to 0)
MDB
012
<Multiplier B>
<Divisor>
Operation Mode
MDB
011
CHAPTER 16 MULTIPLIER/DIVIDER
MDB
010
User’s Manual U16899EJ3V0UD
R/W
MDB
009
<Product>
<Quotient>
MDB
008
Dividend
Higher 16 bits: 0, Lower 16
bits: Multiplier A
MDB
007
MDB
Setting
006
MDB
005
Even in this case, the operation is
<Remainder>
FF66H (MDB0L)
MDB
004
MDB
003
Division result (quotient)
Multiplication result
(product)
MDB
Operation Result
002
MDB
001
MDB
000
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