UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 278

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

<R>
(3) Baud rate generator control register 0 (BRGC0)
276
Address: FF71H After reset: 1FH R/W
BRGC0
Notes 1.
Symbol
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
2.
Be sure to set the base clock so that the following condition is satisfied.
Note the following points when selecting the TM50 output as the base clock.
It is not necessary to enable the TO50 pin as a timer output pin in any mode.
MDL04
TPS01
TPS01
PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty
= 50%.
Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
V
V
V
V
7
0
0
1
1
0
0
0
0
1
1
1
1
1
1
DD
DD
DD
DD
Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
= 4.0 to 5.5 V: Base clock
= 3.3 to 4.0 V: Base clock
= 2.7 to 3.3 V: Base clock
= 2.5 to 2.7 V: Base clock
MDL03
TPS00
TPS00
6
0
1
0
1
0
1
1
1
1
1
1
1
1
1
CHAPTER 13 SERIAL INTERFACE UART0
TM50 output
f
f
f
X
X
X
/2 (5 MHz)
/2
/2
MDL02
3
5
(1.25 MHz)
(312.5 kHz)
5
0
0
0
0
0
0
1
1
1
1
User’s Manual U16899EJ3V0UD
Note 2
10 MHz
8.38 MHz
5 MHz
2.5 MHz (standard products, (A) grade products only)
MDL04
MDL01
4
0
0
1
1
1
0
0
1
1
Base clock (f
MDL03
MDL00
3
0
1
0
0
1
0
1
0
1
XCLK0
) selection
10
26
27
28
29
30
31
k
8
9
MDL02
2
Setting prohibited
f
f
f
f
f
f
f
f
f
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
XCLK0
Selection of 5-bit counter
Note 1
/8
/9
/10
/26
/27
/28
/29
/30
/31
MDL01
output clock
1
MDL00
0